package yycore

import chisel3._
import chisel3.util._
import bus._
import common.Constants._
  
class Frontend extends Module {
  val io = IO(new Bundle(){
    val flush = Input(Bool())
    val imem = new CoreLinkIO(DataBits)
    val out = Decoupled(new InstrPackage)
    val redirect = Flipped(new RedirectIO)
  })

  val s_ifu = Module(new IFU())
  val ibuf = Module(new IBuffer(IBufSize = 4))

  //s_ifu.io.flush := io.flush
  s_ifu.io.imem <> io.imem
  s_ifu.io.redirect <> io.redirect
  
  ibuf.io.flush := io.flush
  ibuf.io.in <> s_ifu.io.out

  io.out <> ibuf.io.out

}
